In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above discussion, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Methods have been described to form planar hybrid substrates with different surface orientations through wafer bonding. In such endeavors, the planar hybrid substrate is obtained mainly through semiconductor-to-insulator, or insulator-to-insulator wafer bonding to achieve pFETs and nFETs on their own optimized crystal orientation for high performance device manufacture. However, at least one type of MOSFET (either pFETs or nFETs) is on a semiconductor-on-insulator (SOI), while the other type of MOSFET is either on a bulk semiconductor or an SOI with a thicker SOI film.
Other technology exists wherein both nFETs and pFETs are fabricated on SOI with the same thickness, but with additional processing steps. SOI devices generally have higher performance than bulk-like devices due to less parasitic capacitance; however, SOI devices have a floating body (i.e., well), whose effect is known to depend on the SOI thickness. Generally, each SOI device is isolated from the other by a shallow trench isolation (STI) region and the buried oxide (BOX). This prior art structure is shown, for example, in FIG. 1. To avoid the floating body effect, each SOI device needs it's own body contact. Such a structure would significantly increase the area of the chip.
On the other hand, the body of MOSFETs fabricated on a bulk silicon substrate is connected through well contacts, which usually are deeper than the STI. Although bulk-devices are isolated from each other by STI, their body contacts can be connected to each other through a common well contact; See, for example, FIG. 2.
In view of the above discussion, there is a need for providing a structure having both pFETs and nFETs on a hybrid substrate with different crystal orientations, wherein the pFET and nFET devices are all bulk-like devices, and wherein each device has a body contact through the well or substrate.